ASICs Eating into GPU Share: Broadcom and Marvell’s Golden Era

For much of the last decade, GPUs have been the default answer to almost any question about high‑performance compute and AI acceleration. They offered flexible parallelism, strong software ecosystems, and a simple story: one architecture, many workloads. That narrative is starting to fragment. In more data‑center racks and custom systems, application‑specific integrated circuits (ASICs) are quietly claiming sockets that might once have gone to GPUs.

This shift is not about GPUs disappearing; they remain central to training and many generalized workloads. Rather, it is about a growing recognition that certain tasks are better served by tightly optimized ASICs that deliver more performance per watt, more predictable behavior, and better alignment with specific application needs. As those ASICs eat into GPU share across networking, storage, and parts of AI inference, Broadcom and Marvell find themselves in the spotlight.

From one‑size‑fits‑many to tailored silicon

GPUs rose to prominence by offering a versatile platform: they could accelerate graphics, machine learning, scientific computing, and more. This versatility made them ideal for an era when workloads were evolving quickly and developers needed a flexible target. As AI and data‑center networking matured, however, patterns solidified. Certain operations repeated at massive scale—packet inspection, routing decisions, encryption, compression, tensor operations for specific inference patterns.

Once those patterns became clear, the economic case for tailored silicon strengthened. ASICs, designed around these well‑defined tasks, could strip away general‑purpose overhead, pack more relevant logic into a given die area, and build data paths that align precisely with how information flows in real deployments. The result: higher throughput, lower latency, and better efficiency for the jobs they target.

Broadcom and Marvell have long histories in such domain‑specific design, especially in networking, storage, and communication. As hyperscalers and large enterprises identify more workloads that fit the ASIC mold, these companies are well positioned to deliver chips that take share from general‑purpose GPUs in certain parts of the stack.

Where ASICs are eating into GPU share

The encroachment of ASICs into GPU territory is most visible in several key domains where workloads are stable and performance constraints are tight.

Data‑center networking and offload. Many tasks once handled by CPUs and, in some cases, assisted by GPUs—such as encryption, packet filtering, load balancing, and telemetry—are moving toward dedicated ASICs. SmartNICs and DPUs embody this trend: they offload network and infrastructure functions into specialized chips, freeing up CPUs and GPUs for pure application compute. Broadcom and Marvell supply a range of networking ASICs that underpin these offload strategies.

Storage and data services. Compression, deduplication, encryption, and erasure coding can be accelerated by GPUs, but ASICs often provide better power and latency characteristics for these repeated, predictable operations. Custom controllers and data‑service accelerators integrate tightly with storage systems, reducing CPU overhead and making it unnecessary to route such tasks through GPU clusters.

AI inference at scale. While GPUs dominate training, certain inference workloads—especially those with fixed architectures and massive volume—are increasingly candidates for ASICs. When the model architecture stabilizes and query patterns are well understood, custom accelerators can outperform general‑purpose GPUs in energy efficiency and cost per query. Network‑connected AI appliances that embed such ASICs sit alongside GPU racks, sharing the inference market.

Telecom and edge networking. In telecom infrastructure and edge gateways, ASICs have long played leading roles. As these systems add AI‑driven traffic management and security features, specialized chips continue to hold ground that might otherwise have been expanded with GPUs.

In each of these domains, GPUs remain valuable for development, flexible experimentation, and some production workloads. However, once a workload’s shape stabilizes, ASICs become attractive alternatives—especially when designed by vendors steeped in networking and communication like Broadcom and Marvell.

Why ASICs are gaining ground now

Several timing factors explain why ASICs are eating into GPU share in this particular period and not earlier.

First, AI and data‑center workloads have matured. Early on, architectures changed frequently, making heavy investment in custom silicon risky. Now, many core patterns—such as transformer‑based models and standard network functions—have shown enough stability to justify ASIC design cycles, which typically span multiple years and require significant upfront cost.

Second, energy and sustainability pressures have intensified. Data‑center operators face rising power costs and stricter efficiency targets. ASICs, by focusing hardware resources on specific operations, can significantly reduce energy consumption for their target workloads compared with general‑purpose alternatives. This efficiency is critical when scaling services to millions of users.

Third, hyperscalers and cloud providers have grown comfortable with heterogeneous hardware. Rather than insisting on a single type of accelerator, they design systems around mixes: GPUs, custom AI chips, offload ASICs, and CPUs. This willingness to integrate multiple silicon types makes it easier to slot ASICs into places where they offer clear advantages without disrupting the overall architecture.

Finally, the business case for ASICs has become clearer. With massive volumes in cloud, networking, and storage, the amortization of design costs over large deployments yields compelling returns. Broadcom and Marvell, with established customer relationships and proven design pipelines, are natural beneficiaries.

Broadcom and Marvell: from plumbing to profit centers

Historically, some observers viewed networking and storage silicon as “plumbing”—essential, but less glamorous than CPUs and GPUs. In the current era, that perception is changing. The logic embedded in switches, NICs, and controllers plays a major role in overall system performance and cost. As ASICs take on more tasks that might once have been handled by general‑purpose compute, the companies that design them move into strategic positions.

Broadcom, with its deep portfolio of switch ASICs, NIC silicon, and custom chips, sits at the core of many hyperscale and enterprise networks. Its products help drive higher bandwidth, better telemetry, and advanced offload features that reduce the need to throw general‑purpose compute at network problems.

Marvell, likewise, operates across networking, storage, and increasingly compute‑related silicon. Its solutions appear in data‑center interconnects, storage controllers, and custom accelerators that form part of AI and cloud infrastructure. As more intelligence migrates into these domains, Marvell’s designs become critical for performance.

In this context, the “golden era” for these companies is not just about higher unit volumes. It is about increased strategic relevance: system architects now treat networking and storage ASICs as central levers in infrastructure planning, not peripheral components. The more workloads that move into their scope, the more these companies share in the growth that might once have been reserved for GPU vendors alone.

Mixed architectures: GPUs and ASICs side‑by‑side

Importantly, ASICs eating into GPU share does not mean systems are choosing one over the other in absolute terms. The prevailing architecture is increasingly mixed: GPUs, ASICs, CPUs, and sometimes FPGAs coexist, each assigned roles that match their strengths.

GPUs remain the go‑to for frontier training, flexible experimentation, and workloads where architectures are evolving. Their software ecosystems, broad developer familiarity, and strong performance across many tasks make them indispensable in R&D and early deployment phases.

ASICs step in where workloads are stable and where offload or specialized acceleration yields significant gains. They handle network, storage, and fixed pattern inference tasks, reducing the burden on GPUs and CPUs. In some cases, they form the backbone of dedicated appliances—AI inference boxes, security gateways, storage arrays—that sit alongside general‑purpose compute clusters.

System designers increasingly view their hardware choices as a portfolio problem: allocate GPU, ASIC, and CPU resources to minimize cost and maximize performance across a spectrum of workloads. In such portfolios, Broadcom and Marvell’s chips play rising roles in keeping the overall system efficient.

Design philosophy: programmable enough, but not too much

One of the key philosophical differences between GPUs and ASICs lies in programmability. GPUs offer wide programmability: a general parallel architecture that can be targeted by many kinds of code. ASICs traditionally bake in specific functions, limiting flexibility. The modern trend blurs this distinction somewhat.

Contemporary ASICs in networking and AI increasingly include programmable elements—embedded cores, configurable pipelines, and domain‑specific instruction sets. They are “programmable enough” to adapt to evolving protocols and algorithms, but not so general‑purpose that they sacrifice the efficiency advantages that come from specialization.

Broadcom and Marvell design chips with this balance in mind. Switch and NIC ASICs often include flexible tables and logic that can be programmed to support new protocols or telemetry schemes, while still leveraging hardware‑accelerated paths for core functions. AI‑related ASICs may support different model variants within a constrained space, offering some flexibility without becoming fully general‑purpose GPUs.

This design philosophy helps explain why ASICs can eat into GPU share without forcing customers into rigid architectures. Buyers gain specialization where it matters, with enough adaptability to avoid rapid obsolescence.

Implications for GPU vendors and ecosystem evolution

ASICs’ growing role naturally prompts questions about how GPU vendors respond. In practice, GPU companies adjust strategies by emphasizing the domains where their strengths remain foundational and by exploring ways to coexist with or complement ASICs.

They continue to push performance and scalability for training, where the flexibility and massive parallelism of GPUs are hard to fully replace. They also invest in software ecosystems that make GPUs attractive for new and evolving workloads, aiming to stay at the center of innovation rather than only serving established use cases.

At the same time, GPU vendors may collaborate with ASIC‑centric companies or integrate ASIC‑like features into their own offerings. For example, they can support tighter integration with offload engines, expose APIs that allow network and storage ASICs to work more smoothly with GPU clusters, and explore semi‑custom configurations for key customers.

For the broader ecosystem, this means a richer diversity of hardware options and a more nuanced division of labor. Developers and architects must understand both GPU and ASIC capabilities to design optimal systems, and tools emerge to abstract some of that complexity while still exposing knobs for precise tuning.

How buyers should think about ASIC vs. GPU allocation

Organizations planning AI and data‑center infrastructure in this “golden era” of ASICs can benefit from a structured approach when deciding where ASICs and GPUs fit.

First, they can map workloads into categories: frontier training, flexible experimentation, stable inference, network and storage services, and edge deployments. Each category suggests different hardware priorities—flexibility versus efficiency, latency versus throughput, programmability versus specialization.

Second, they can evaluate where offload makes economic and operational sense. If GPUs or CPUs spend significant cycles on networking, encryption, or storage tasks, ASICs that offload those functions may free resources for core application compute and reduce overall costs.

Third, they can consider vendor ecosystem maturity and support. Broadcom and Marvell’s ASICs, for example, often come with reference designs, integration support, and long‑term roadmaps that help reduce deployment risk. Similarly, GPU vendors provide rich software tools. Aligning hardware choices with ecosystems that match internal capabilities is vital.

Finally, they can plan for heterogeneity explicitly—designing systems where GPUs and ASICs coexist and are orchestrated intelligently. That might involve using DPUs or smartNICs as intermediaries, building scheduling systems that understand different accelerator types, and ensuring observability across the diverse hardware stack.

Approached this way, the question becomes not “ASICs or GPUs?” but “where do ASICs, GPUs, and other silicon types best complement each other?”

Conclusion: a broader definition of high‑performance silicon

The story of ASICs eating into GPU share and ushering in a golden era for Broadcom and Marvell illustrates a broader shift in how we think about high‑performance silicon. The era of a single dominant accelerator is giving way to one where specialized chips carve out territory alongside general‑purpose platforms, each serving the workloads they are best suited for.

GPUs remain vital engines of training and innovation, but ASICs now carry a growing share of work in networking, storage, and stable inference, changing how data centers are built and optimized. Companies that have long mastered domain‑specific silicon—like Broadcom and Marvell—are stepping into more prominent roles as infrastructure architects put specialization at the heart of their designs.

As this trend continues, the semiconductor landscape will look increasingly heterogeneous and nuanced. Success will belong not just to the fastest general‑purpose chip, but to the most well‑balanced system of GPUs, ASICs, CPUs, and other accelerators working together—each playing its role in a sophisticated, highly optimized digital infrastructure.